In wired communication the clock, i.e., the timing information, is extracted from the received data signal, including both frequency and phase of the clock. The function that extracts clock and timing information from the received data signal is commonly known as clock and data recovery (CDR). In applications where provision of an accurate clock is not affordable, the initial frequency of the receiver can be substantially far from the clock frequency used for the transmission of data. This is commonly known as reference-less clock operation as the receiver lacks a reliable and accurate source of clock. In this case, frequency locking becomes a difficult and important task. One efficient method for reference-less clock operation is the Pottbäcker scheme. This scheme uses a binary phase-frequency detector (PFD) that helps to bring its phase locked loop (PLL) into frequency-phase lock. The employed PFD is designed for binary non-return-to-zero (NRZ) signals.
There are applications in which multilevel signaling like PAM4, PAM8 and so on has proven to be advantageous over binary NRZ in terms of increased reach, i.e. longer cable, improved data rate, and/or reduced consumed power. However, such an increase in the number of signal levels effectively causes a wider span of zero-crossing points in the received data signal. This in turn causes degradation in PFD performance as it is solely relying on cleanness of the signal in its zero-crossing points. Despite this degradation, the NRZ based PFD is still useful in a Pottbäcker scheme and provides frequency locking, albeit at a slower rate. However after frequency lock, the NRZ based PFD has unsatisfactory performance in phase tracking and leaves a large amount of clock jitter, which substantially reduces the steady state performance of the receiver.